Error detection and correction system



March 13, 1962 A. c. REYNOLDS, JR 3,024,992

ERROR DETECTION AND CORRECTION SYSTEM Original Filed Feb. 26,1957

l8 Sheets-Sheet l 1 F/G.

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ERROR DETECTION AND CORRECTION SYSTEM March 13, 1962 A. c. REYNOLDS, JR3,024,992

ERROR DETECTION AND CORRECTION SYSTEM 18 Sheets-Sheet 3 Original Filed FlNl/ENTOR A. C. REYNOLDS JR. av

Cm N ATTORNEY March 13, 1962 A. c. REYNOLDS, JR 3,024,992

ERROR DETECTION AND CORRECTION SYSTEM 18 Sheets-Sheet 4 Original FiledFeb 9 OE OF 009 x235 v hm ME; moon wk Mk8 zoiuw mm F5238 /Nl/EN7OR A. C.REYNOLDS JP.

A T TORNE V March 13, 1962 A. C. REYNOLDS, JR

ERROR DETECTION AND CORRECTION SYSTEM Original Filed Feb. 26, 1957 FIG./7

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ERROR DETECTION AND CORRECTION SYSTEM Original Filed Feb. 26, 1957 18Sheets-Sheet 6 O O O O O O O O O 8 a 8 2% a a g a 2 INVENTOR 06 A. CREYNOLDS JR. 9 g 3 2 8 K, E 5v u EH. Q 9' 2 2 [I t u. u.

A 7'7'ORNE V March 13, 1962 A. c. REYNOLDS, JR 3,024,992

ERROR DETECTION AND CORRECTION SYSTEM 18 Sheets-Sheet 7 Original FiledFeb. 26, 1957 //v VENTOR A. C. REVNOL 05 JR. BY

| @OK 20mm A TTORNEK March 13, 1962 A. c. REYNOLDS, JR 3,024,992

ERROR DETECTION AND CORRECTION SYSTEM Original Filed Feb. 26, 1957 18Sheets-Sheet 8 AAA O JMO 4 0 ATTORNFV March 13, 1962 A. c. REYNOLDS, JR3,024,992

ERROR DETECTION AND CORRECTION SYSTEM Original Filed Feb. 26, 1957 18Sheets-Sheet ll FIG26 F'IG.27

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A T TORNE V March 13, 1962 A. c. REYNOLDS, JR 3,024,992

ERROR DETECTION AND CORRECTION SYSTEM Original Filed Feb. 26, 1957 18Sheets-Sheet 12 COUNTER SELECTION PULSES BIT PULSES 55%? E CCT. 77 F /9H653 BIT STOR /28 FOUR WIRE BIT TRUNK 76 l ,4. C. REYNOLDS JR. 8V

March 13, 1962 A. c. REYNOLDS, JR 3,024,992

ERROR DETECTION AND CORRECTION SYSTEM Original Filed Feb. 26, 1957 18Sheets-Sheet 13 OUTPUT BITS EXTENTED T0 FIGBI M/l/ENTOF? ,4. C. REYNOLDSJR.

March 13, 1962 A. c. REYNOLDS, JR 3,024,992

ERROR DETECTION AND CORRECTION SYSTEM Original Filed Feb. 26, 1957 18Sheets-Sheet 14 lNl/ENTOR A. C. REYNOLDS J/?.

ATTOPNEV March 13, 1962 A. CREYNOLDS, JR

ERROR DETECTION AND CORRECTION SYSTEM Original Filed Feb. 26, 1957 18Sheets-Sheet 15 FlG.3l FIGBZ F7630 BY M/l ENTOR A. C. REYNOLDS JR.

A T TOR/VL V March 13, 1962 A, c. REYNOLDS, JR 3,024,992

ERROR DETECTION AND CORRECTION SYSTEM WV- 5 A m w CHECK TIME wi T //vI/EN TOP A. C. REYNOLDS JR.

United Etates Patent @fiee 3,024,092 Patented Mar. 13, 1962 7 Claims.(El, 235-174) This is a division of application Serial Number 642,509,Patent No. 2,969,912, filed February 26, 1957 for improvements in ErrorDetecting and Correcting Circuits.

This invention relates to means for detecting and correcting errors intransmitted information and particularly relates to electronicregistering means for receiving, changing, accumulating and storing thecoded manifestations of decimal digits.

An object of the invention is to provide supervisory means for examiningcoded items of information, each accompanied by its unique checkingitems, and to delay the further processing movement thereof until adetected error can be corrected or until an alarm may be given throughdisabling means provided to report a non-correctable error.

The invention consists in general of a means for handling information intransit. Each item of information, which, by way of example, may be aten digit number before entry into a processing machine, has certaincheck digits derived therefrom and these check digits are thereafterassociated with this ten digit number and become part of the word. Onegroup of these check digits consists of the decimal equivalent of thebinary number formed by the selection of one of two distinguishablecharacteristics from each of the binary code representations of each ofthe decimal digits of the said ten digit number.

For purposes of explanation an example will be discussed in great detailthroughout this specification. It will be assumed that the decimalnumber the least significant position bit of each group, thus producingthe binary number 1 1 1 l 1 0 0 1 0 which, translated into its decimalequivalent, becomes and which, expressed in the binary decimal notation(for purposes which will appear hereinafter), becomes Another uniquecheck digit is derived by using the units digit of the sum of the digitsof the said number, this being known as the sum modulo 10 of the number.The sum of so that the digit 4 is a derived check digit which along withthe number 0754 is associated with the said number and which accompaniesthe said number in its movements through the processing machine. Thisitem of information is precalculated so that when the number and itscheck digits are moved about they appear as and this is expressed in thebinary decimal code so that it forms a succession of fifteen four placecodes which may be transmitted over a conventional four wire bit trunk.It will be assumed that the means for successively entering andtransmitting each of these codes over such a four wire bit trunk inwhich the bits are simultaneously moved is entirely conventional.

The invention consists of means for successively gating these fifteendigits into fifteen digit stores for processing which comprises twoprincipal operations. First the four check digits 0754 are translatedinto an equivalent binary number and this is compared with the ten digitnumber which has actually been stored. Let us assume that in processingand by reason of some random error, the second digit 6 has become a 7.The comparison would then be between and it will at once be apparentthat there is an error in the second place.

At the same time and during the entry of the ten digits of this word,these ten digits are summed step by step and the sum of the digits ofthe number containing the error comes out to be 45 so that the summodulo 10, which is 5, fails to compare with the last (fifteenth place)check digit 4.

These two check failures then immediately start a correcting operation.This consists of opening a gate to the second place digit store and theintroduction thereinto of a train of correcting pulses andsimultaneously therewith the introduction into the means for summing thedigits of exactly the same number of pulses. This has the effect ofadvancing the record in the second place digit store successivelythrough the values 8, 9, 0, 1, 2, 3, 4, 5 and 6 and simultaneouslytherewith of advancing the record in the summing device successivelythrough the values 46, 47, 48, 49, 50, 51, 52, 53 and 54. When the lastvalue 54 is reached, its units value 4 will compare exactly with thelast place check digit and this Will bring about a circuit changeconstituting a satisfaction signal which will stop further correctionoperations and will cause the corrected ten digit number to betransferred to a use circuit, such as an arithmetic section of acomputer.

It should be noted that if no error had been detected the said ten digititem of information would have been immediately passed along to the saiduse circuit.

From the above discussion, and further by way of example, it will appearthat with circuits and apparatus hereinabove set forth, an error can bedetected only if it appears in the 1 bit place of some one of the digitsforming the ten digit word, for otherwise the four digit check 0754would remain the same while only the sum modulo 10 check digit wouldchange. Since under these conditions there would be an absence ofinformation necessary for the operation of the proper gate to the storecontaining the digit in error, this will be known as a noncorrectableerror and can only result in an alarm.

It may also be noted that where the four digit check number shows adeviation but the sum modulo 10 check digit shows no deviation, thisalso constitutes a noncorrectable error for no information exists whichwill control the number of correction pulses which must be introducedinto the store or stores containing an erroneous number. Where more thanone erroneous decimal digit exists in store then a non-correctable errorwill be reported, for while the four digit check may lead to thediscovery of the location of such multiple errors, the single digit summodulo check digit cannot report the diifering magnitude of two or moreerrors.

While the system outlined above is particularly useful for the detectionand correction of errors occurring in the transmission of data in pulseform, e.g. transmission of a number of pulses in seriatirn correspondingto the value of a digit as in the telephone dial system, it is to beunderstood that the present invention contemplates means for detectingand correcting errors occurring in data transmitted in any digital form.

When transmitting the representation of a digit by a number of pulsescorresponding to the value of a digit, an error changing the transmittedvalue by more than one is far less likely than an error changing thetransmitted value by one. For example, when transmitting the digit byseven pulses in seriatim, it is far less likely that more than 8 or lessthan 6 pulses will be received than that 8 or 6 pulses will be received,the former consti-tuting a double error while the latter constitutes asingle error. The system outlined above is quite accurate for datatransmitted in pulse form. This data, of course, may be subsequentlytranslated into the binary coded decimal form or into any other codedform. if, however, the transmission is over four parallel wires in thebinary coded decimal form, for example, then the check digits would bederived from parity or redundant bits generated in any manner well knownin the art. Thus, the even parity check bit for the digit 7 might beformed as follows. in the binary coded decimal form, the digit 7 isrepresented as 0111 and the sum of the bits is 3, or odd, and thus a 1is the even parity check bit. That is, 1 must be added to 3 to make thesum even. The binary check number derived from the example in thismanner would thus be which binary number translates into the decimalnumber This number with the modulo 10 sum of the digits, 4, is now usedin the same manner as explained above, and is transmitted as It is to benoted that, in both the above examples, two mutually exclusivecharacteristics of each digit have been chosen as the basis for formingthe binary check number, in the first case the odd or evencharacteristic of the decimal number and in the second case the odd oreven characteristic of the sum of the bits used in the binary coded formof such decimal number. The binary check number so formed has beentranslated into the decimal system of notation for transmission with theinformation carrying digits. It is to be noted further that theinvention is not limited to the decimal system of: notation since thebinary check number can be translated into any system of notation asdesired, for example, base 36 or larger for handling both alphabetic andnumeric data.

It is further to be noted that in the first example given a singlerandom error in the 1 bit place may be specifically detected andcorrected when the odd or even value of a decimal digit is thecharacteristic used as a control.

xperience with the transmission of information particularly in greatdigital information handling networks such as the telephone system andthe digital computers has shown that the occurrence of such singlerandom errors is extremely rare and that the occurrence of a doubleerror is so extraordinarily rare that provision for its detecuon isalmost never made. However, the detection 4- and correction of an errorin the 1 bit place alone will detect only 25% of the random errors forwhich it is believed provision should be made for it is just as likelythat a random error may occur in the 2 bit, the 4 bit, or the 8 bitplace as it is that such an error may occur in the 1 bit place.

A feature of the invention therefore is a means for detecting andcorrecting a single error which may occur at random in any one of thefour places of the binarydecimal code. Consider the digit 6 which isexpressed in the binary-decimal code as 0110. The sum of the bits iseven and a random error in any one of these four places will change thesum of odd. If, by way of example, through a random error this code istransmitted as 0010, an error in the 4 bit place, the change from odd toeven would change the synthesized binary number from Although this lastnumber translates to the decimal number 0796, this translation isimmaterial since it is the comparison of these two ten place binarynumbers which is used to locate the error and since in the comparisoncircuits inequality appears in the second place (the 256 bit place) isis this digit as recorded at the distant end that must be corrected.

From a practical standpoint the code 0010 is equivalent to the decimalvalue 2. This changes the sum of the bits from even to odd and pointsout the location of an error as being in the second digital place. Thiswill require the transmission of 4 correcting pulses to advance theregister from 0010 through the value 0011 to the correct value 0110. Theerroneous code 00 10 which is transmitted being equal to the decimalvalue 2, will cause the sum of the decimal digits to be 40 instead ofthe proper sum 44, so that as the 4 correcting pulses are transmitted tothe second place register, they also advance the modulo 10 summingdevice from the value 40 through the value 41 to the value 44, whichgives the sum modulo 10 value of 4 and which compares exactly with themagnitude digit 4.

However, if through random error the code 0110 is sent as 0100, thevalue of the sum of the bits is changed from even to odd and thecorrection will take place by the transmission of 2 correcting pulses toadvance the second place register from the value 0100 successivelythrough the value 0101 to 0110. Since the code represents the decimalvalue 4, the sum of the digits calculated on the receipt of these codeswill turn out to be 42 showing the sum modulo ten equal to 2 and sincethis does not compare to the digit 4 transmitted, these two correctingpulses will also run the modulo 10 summing device successively throughthe value 43 until it reaches the value 44- to exhibit the value 4 whichcompares with the magnitude check digit.

Again, let it be assumed that by random error, the code 0110 is sent as0111. In this case the sum of the bits has been changed from even toodd. The four digit location code reports an error in the second placeand the modulo ten device reports a sum of 45 or a value 5 instead ofthe value 4 carried by the magnitude code.

In this case nine correction pulses will be transmitted to run thesecond place register from the value 0111 successively through thevalues 1000, 1001, 0000, 0001, 0010, 0011, 0100, 0101 until it reachesthe value 0110, the modulo 10 summing device advancing simultaneouslyfrom the value 45, through the values 46, 47, 48, 49, 50, 51, 52, 53until it reaches the value 54.

By thus using a summing network to derive a parity pulse, that is, todifferentiate between an even and an odd sum of the number of bitstransmitted, it will be seen that of the single errors which stillproduce a legitimate code may be detected and corrected.

